Synchronous Simplex ARQ using the error correcting 7 bit ITA 3 alphabet. Two stations use the same frequency, working as ISS (transmitting) and IRS (receiving) stations. Every odd cycle all the bits inverted.

With variable block length of 3, 9 or 22 characters the repetition cycle is as follows,

450 msec: 3 characters at 7 bits = 210 msec, followed by 210 msec pause
900 msec: 9 characters at 7 bits = 630 msec, followed by 270 msec pause
1800 msec: 22 characters at 7 bits = 1540 msec, followed by 260 msec pause

 Click here for a typical ARQ - SWE sound